Daily activities As part of our team you will contribute to requirements analysis and decomposition, design and implement the verification scenarios using System Verilog and UVM of new FPGA functionalities for 5G telecommunication system following the...>
Daily activities As part of our team you will contribute to requirements analysis and decomposition, design and implement the verification scenarios using System Verilog and UVM of new FPGA functionalities for 5G telecommunication system following the...>
Design, model and code solutions that fit the problem domain Take responsibility for all development work and ownership of quality control Work with other developers, testers, Scrum Master, Product Owner and other people involved Generate ideas with other...>
